K4S643232C
CMOS SDRAM
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
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The K4S643232C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
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3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle
ORDERING INFORMATION
Part NO.
K4S643232C-TC/L55
K4S643232C-TC/L60
K4S643232C-TC/L70
K4S643232C-TC/L80
K4S643232C-TC/L10
Max Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
Interface
Package
LVTTL
86
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
LWE
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
Output Buffer
Sense AMP
Row Decoder
ADD
Row Buffer
Refresh Counter
DQi
Column Decoder
Col. Buffer
LCBR
LRAS
Address Register
CLK
512K x 32
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
