-5,-5L:Preliminary
MITSUBISHI LSIs M2V64S20DTP-5,-5L,-6,-6L,-7,-7L
M2V64S30DTP-5,-5L,-6,-6L,-7,-7L
SDRAM (Rev.4.2)
M2V64S40DTP-5,-5L,-6,-6L,-7,-7L
Jun.'01
(4-BANK x 4,194,304-WORD x
4-BIT)
(4-BANK x 2,097,152-WORD x
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Some of contents are described for general products and are subject to change w ithout notice.
DESCRIPTION
M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M 2V64S20DTP, M2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up
to 166MHz for -5, 133MHz for -6, 100MHz for -7, and are suitable for main memory or graphic
memory in computer systems.
FEATURES
M2V64S20/30/40DTP
ITEM
tCLK
tRAS
-5
-6
-7
Clock Cycle Time
(Min.)
6ns
7.5ns
10ns
(Min.)
(Min.)
42ns
45ns
50ns
tRCD
Active to Precharge Command Period
Row to Column Delay
15ns
20ns
20ns
tAC
Access Time from CLK
(Max.) (CL=3)
tRC
Active Command Period
(Min.)
5.4ns
60ns
5.4ns
67.5ns
6ns
70ns
V64S20D
Icc6
Operation Current
Self Refresh Current
(Max.)
(Single Bank)
90mA
75mA
70mA
V64S30D
90mA
75mA
70mA
V64S40D
Icc1
100mA
85mA
80mA
1mA
1mA
1mA
(Max.)
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:166MHz<3-3-3>, -6:133MHz<3-3-3>, -7:100MHz<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQM L and DQMU for M2V64S40DTP
- Random column access
- Auto precharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
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