MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8ĆBit Shift Register
MC10E141
MC100E141
The MC10E/100E141 is an 8-bit full-function shift register. The E141
performs serial/parallel in and serial/parallel out, shifting in either
direction. The eight inputs D0 – D7 accept parallel input data, while
DL/DR accept serial input data for left/right shifting. The Qn outputs do
not need to be terminated for the shift operation to function. To minimize
noise and power, any Q output not used should be left unterminated.
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700MHz Min. Shift Frequency
8-BIT SHIFT
REGISTER
8-Bit
Full-Function, Bi-Directional
Asynchronous Master Reset
Pin-Compatible with E241
Extended 100E VEE Range of – 4.2V to – 5.46V
75kΩ Input Pulldown Resistors
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Pinout: 28-Lead PLCC (Top View)
SEL0
DL
D7
D6
D5
VCCO
Q7
25
24
23
22
21
20
19
SEL1
26
18
Q6
CLK
27
17
Q5
MR
28
16
VCC
VEE
1
15
NC
DR
2
14
VCCO
D0
3
13
Q4
D1
4
FUNCTION TABLE
SEL0
5
6
7
8
9
10
D3
D4
VCCO
Q0
Q1
L
H
L
H
Function
Load
Shift Right (Dn to Dn+1)
Shift Left (Dn to Dn –1)
Hold
PIN NAMES
Pin
Function
D0 – D7
DL, DR
SEL0, SEL1
CLK
Q0 – Q7
MR
11
D2
L
L
H
H
Q3
12
SEL1
Q2
* All VCC and VCCO pins are tied together on the die.
Parallel Data Inputs
Serial Data Inputs
Mode Select In Inputs
Clock
Data Outputs
Master Reset
EXPANDED FUNCTION TABLE
Function
DL
DR
SEL0
SEL1
MR
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Load
Shift Right
X
X
X
L
L
L
L
H
L
L
Z
Z
D0
L
D1
Q0
D2
Q1
D3
Q2
D4
Q3
D5
Q4
D6
Q5
D7
Q6
X
H
L
H
L
Z
H
L
Q0
Q1
Q2
Q3
Q4
Q5
L
X
H
L
L
Z
L
Q0
Q1
Q2
Q3
Q4
Q5
L
H
X
H
L
L
Z
Q0
Q1
Q2
Q3
Q4
Q5
L
H
Hold
X
X
H
H
L
Z
Q0
Q1
Q2
Q3
Q4
Q5
L
H
Reset
X
X
X
X
H
X
H
X
L
H
Z
X
Q0
L
Q1
L
Q2
L
Q3
L
Q4
L
Q5
L
L
L
H
L
Shift Left
7/96
© Motorola, Inc. 1996
2–1
REV 3
