MC10186
Hex D Master-Slave
Flip-Flop with Reset
The MC10186 contains six high–speed, master slave type “D”
flip–flops. Clocking is common to all six flip–flops. Data is entered
into the master when the clock is low. Master to slave data transfer
takes place on the positive–going Clock transition. Thus, outputs may
change only on a positive–going Clock transition. A change in the
information present at the data (D) input will not affect the output
information any other time due to the master–slave construction of this
device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT.
RESET ONLY FUNCTIONS WHEN CLOCK IS LOW.
• PD = 460 mW typ/pkg (No Load)
• ftoggle = 150 MHz (typ)
• tr, tf = 2.0 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10186L
AWLYYWW
1
16
PDIP–16
P SUFFIX
CASE 648
LOGIC DIAGRAM
MC10186P
AWLYYWW
1
5
D0
D1
2
3
6
D2
4
7
1
Q0
PLCC–20
FN SUFFIX
CASE 775
Q1
A
WL
YY
WW
Q2
10186
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
13 Q3
D3 10
1
16
VCC
Q0
2
15
Q5
Q1
3
14
Q4
Q2
4
13
Q3
D0
5
12
D5
15 Q5
D1
6
11
D4
VCC = PIN 16
VEE = PIN 8
D4
RESET
D2
7
10
D3
VEE
8
9
CLOCK
14 Q4
11
D5 12
CLOCK 9
RESET 1
CLOCKED TRUTH TABLE
R
C
D
Qn + 1
L
L
X
Qn
L
H*
L
L
L
H*
H
H
H
L
X
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
L
ORDERING INFORMATION
Device
January, 2002 – Rev. 7
1
25 Units / Rail
PDIP–16
25 Units / Rail
MC10186FN
© Semiconductor Components Industries, LLC, 2002
Shipping
CDIP–16
MC10186P
*A clock H is a clock transition
from a low to a high state.
Package
MC10186L
PLCC–20
46 Units / Rail
Publication Order Number:
MC10186/D
