Order this document by MC145202–1PP/D
MC145202-1
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2.0 GHz PLL Frequency
Synthesizer
The MC145202–1 is pin–for–pin compatible with the previous generation
MC145200, MC145201, and MC145202. Table 1 highlights the different
features in these four devices. The MC145202–1 is recommended for new
designs, and also offers improved suppression of reference sideband spurs.
The counters are programmed via a synchronous serial port which is SPI
compatible. The serial port is byte-oriented to facilitate control via an MCU.
Due to the innovative BitGrabber Plus™ registers, the MC145202–1 may be
cascaded with other peripherals featuring BitGrabber Plus without requiring
leading dummy bits or address bits in the serial data stream. In addition,
BitGrabber Plus peripherals may be cascaded with existing BitGrabber™
peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor
tied from the Rx pin to ground. This current can be varied via the serial port.
Slew–rate control is provided by a special driver designed for the REFout
pin. This minimizes interference caused by REFout.
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external
crystal and a programmable reference output. The R, A, and N counters are
fully programmable. The C register (configuration register) allows the part to
be configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from
being loaded into the counters, on–board circuitry synchronizes the update
of the A register if the A or N counters are loading. Similarly, an update of the
R register is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented
to the three counters (R, A, and N) simultaneously.
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PLL FREQUENCY
SYNTHESIZER
SEMICONDUCTOR
TECHNICAL DATA
1
Operating Supply Voltage Range (VDD, VCC, VPD Pins): 2.7 to 5.5 V
Current Source/Sink Phase Detector Output:
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V
Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
R Counter Division Range: 1 and 5 to 8191
DT SUFFIX
PLASTIC PACKAGE
CASE 948D
(TSSOP–20)
20
1
PIN CONNECTIONS
REFout
LD
1
2
20 REFin
19 Din
φR
φV
3
18 CLK
4
17 ENB
VPD
PDout
5
16 Output A
6
15 Output B
Gnd
7
Rx
8
14 VDD
13 Test 2
Test 1
9
Maximum Operating Frequency: 2000 MHz @ –10 dBm
Operating Supply Current: 4 mA Nominal at 3.0 V
F SUFFIX
PLASTIC PACKAGE
CASE 751J
(SO–20)
20
12 VCC
11 fin
fin 10
(Top View)
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 4 Mbps
Output A Pin, When Configured as Data Out, Permits Cascading of
Devices
Two General–Purpose Digital Outputs:
Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for
Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.
MOTOROLA RF/IF DEVICE DATA
EVALUATION KIT
The P/N TBD, which contains hardware and
software, will be available.
ORDERING INFORMATION
Device
MC145202F1
MC145202DT1
Operating
Temperature Range
TA = –40 to 85°C
© Motorola, Inc. 1999
Package
SO–20
TSSOP–20
Rev 0
1
