Freescale Semiconductor, Inc.
Order number: MC88LV915T
Rev 3, 08/2001
TECHNICAL DATA
Low Voltage Low Skew CMOS PLL
Clock Driver, 3-State
MC88LV915T
The MC88LV915T Clock Driver utilizes phase-locked loop technology to lock
LOW SKEW CMOS
its low skew outputs' frequency and phase onto an input reference clock. It is
PLL CLOCK DRIVER
designed to provide clock distribution for high performance PC's and
workstations.
The PLL allows the high current, low skew outputs to lock onto a single clock
input and distribute it with essentially zero delay to multiple components on a
board. The PLL also allows the MC88LV915T to multiply a low frequency input
clock and distribute it locally at a higher (2X) system frequency. Multiple
88LV915's can lock onto a single reference clock, which is ideal for applications
when a central system clock must be distributed synchronously to multiple
boards (see Figure 6).
FN SUFFIX
Five “Q” outputs (Q0-Q4) are provided with less than 500 ps skew between
28-LEAD PLCC PACKAGE
their rising edges. The Q5 output is inverted (180° phase shift) between their
CASE 776-02
rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs.
The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at
1/2 the “Q” frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in detail the different
feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the “Q” outputs to the
SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide-by in the feedback path of the PLL. It selects between divide-by-1 and
divide-by-2 of the VCO before its signal reaches the internal clock distribution section of the chip (see Figure 2). In most applications
FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2) will allow the VCO
to run in its optimal range (>20MHz).
In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board-level testing
(see Applications Information for All Versions).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0-Q4, Q5 and Q/2 into a high impedance state (3-state). After the
OE/RST pin goes back high Q0-Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go
low if phase-lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees a
SYNC signal and full 5V VCC.
Features
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Five Outputs (Q0-Q4) with Output-Output Skew < 500 ps each being phase and frequency locked to the SYNC input
The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD
specification, which defines the part-to-part skew)
Input/Output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available
Input frequency range from 5MHz - 2X_Q FMAX spec.
Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL-level compatible. ±88mA IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge
Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All
outputs can go into high impedance (3-state) for board test purposes
Lock Indicator (LOCK) accuracy indicates a phase-locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
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FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
