MOTOROLA
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by MCM6226BB/D
SEMICONDUCTOR TECHNICAL DATA
MCM6226BB
128K x 8 Bit Static Random
Access Memory
XJ PACKAGE
400 MIL SOJ
CASE 857A–02
The MCM6226BB is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6226BB is equipped with both chip enable (E1 and E2) and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems.
The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount
SOJ packages.
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•
•
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Single 5 V ± 10% Power Supply
Fast Access Times: 15/17/20/25/35 ns
Equal Address and Chip Enable Access Times
All Inputs and Outputs are TTL Compatible
Three State Outputs
Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC
EJ PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
NC
1
32
VCC
A
2
31
A
A
3
30
E2
A
4
29
W
A
5
28
A
A
6
27
A
BLOCK DIAGRAM
A
A
7
26
A
A
A
8
25
A
A
A
9
24
G
A
A
A
A
10
23
A
A
11
22
E1
A
MEMORY MATRIX
512 ROWS x
2048 COLUMNS
ROW
DECODER
12
21
DQ
DQ
DQ
DQ
W
G
DQ
15
18
DQ
16
17
DQ
COLUMN I/O
INPUT
DATA
CONTROL
E1
E2
DQ
19
DQ
A
20
14
VSS
A
13
DQ
A
PIN NAMES
COLUMN DECODER
A
A
A
A
A
A
A
A
A . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . Chip Enables
DQ . . . . . . . . . . . . . Data Inputs/Outputs
NC . . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 2
10/31/96
© Motorola, Inc. 1996
MOTOROLA FAST SRAM
MCM6226BB
1
