MOTOROLA
Order this document
by MTP15N06V
SEMICONDUCTOR TECHNICAL DATA
Designer's
™ Data Sheet
MTP15N06V
TMOS V
Power Field Effect Transistor
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
TM
D
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
G
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and
TMOS E–FET
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDSS
VDGR
60
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 50 µs)
VGS
VGSM
± 20
± 25
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
15
8.7
45
Adc
Total Power Dissipation @ 25°C
Derate above 25°C
PD
55
0.5
Watts
W/°C
TJ, Tstg
EAS
– 55 to 175
°C
113
mJ
RθJC
RθJA
2.73
62.5
°C/W
TL
260
°C
Rating
Drain–Source Voltage
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
