16Mb: x16
IT SDRAM
SYNCHRONOUS
DRAM
MT48LC1M16A1 SIT - 512K x 16 x 2 banks
INDUSTRIAL TEMPERATURE
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/sdramds.html
FEATURES
PIN ASSIGNMENT (Top View)
50-Pin TSOP
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
• Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2 and 3
• Industrial temperature range: -40°C to +85°C
OPTIONS
VDD
DQ0
DQ1
VssQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VssQ
DQ6
DQ7
VDDQ
DQML
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
VDD
MARKING
• Configuration
1 Meg x 16 (512K x 16 x 2 banks)
Note: The # symbol indicates signal is active LOW.
1M16A1
• Plastic Package - OCPL*
50-pin TSOP (400 mil)
-6
-7
-8A
• Refresh
2K or 4K with Self Refresh Mode at 64ms
16MB (X16) SDRAM PART NUMBER
S
• Operating Temperature
-40°C to +85°C
1 Meg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0-A10)
2 (BA)
256 (A0-A7)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
TG
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
8ns (125 MHz)
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VssQ
DQ9
DQ8
VDDQ
NC
DQMH
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IT
PART NUMBER
MT48LC1M16A1TG SIT
ARCHITECTURE
1 Meg x 16
KEY TIMING PARAMETERS
Part Number Example:
SPEED
CLOCK
-6
-7
-8A
166 MHz
143 MHz
125 MHz
MT48LC1M16A1TG-7SIT
ACCESS TIME
CL = 3**
5.5ns
5.5ns
6ns
SETUP
HOLD
2ns
2ns
2ns
1ns
1ns
1ns
*Off-center parting line
**CL = CAS (READ) latency
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
