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SN74LS75N
SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. The SN54 / 74LS75 features complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAMS DIP (TOP VIEW) Q0 Q1 16 Q1 14 15 E0–1 GND 13 12 Q2 Q2 11 10 J SUFFIX CERAMIC CASE 620-09 Q3 9 16 1 SN54 / 74LS75 1 Q0 2 D0 Q0 14 3 D1 Q1 13 4 5 E2–3 VCC E0–1 GND 12 11 NC 10 6 D2 Q2 9 16 8 Q3 7 D3 N SUFFIX PLASTIC CASE 648-08 1 Q3 8 16 1 D SUFFIX SOIC CASE 751B-03 SN54 / 74LS77 1 D0 2 D1 3 E2–3 4 VCC 5 D2 6 D3 PIN NAMES J SUFFIX CERAMIC CASE 632-08 7 NC 14 1 LOADING (Note a) HIGH D1–D4 E0–1 E2–3 Q1–Q4 Q1–Q4 Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) LOW 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a) 1 Unit Load (U.L.) = 40 µA HIGH. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 TRUTH TABLE (Each latch) ORDERING INFORMATION tn tn + 1 D H L Q H L NOTES: tn = bit time before enable negative-going transition tn+1 = bit time after enable negative-going transition SN54LSXXJ SN74LSXXN SN74LSXXD FAST AND LS TTL DATA 5-1 Ceramic Plastic SOIC
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