OBSOLETE
1 MEG x 16
FPM DRAM
FPM DRAM
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional self refresh (S) for low-power data
retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
OPTIONS
•
PIN ASSIGNMENT (Top View)
42-Pin SOJ
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
MARKING
Voltage 1
3.3V
5V
LC
C
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
44/50-Pin TSOP
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
NOTE: The # symbol indicates signal is active LOW.
1 MEG x 16 FPM DRAM PART NUMBERS
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
None
S2
• Operating Temperature Range
Commercial (0oC to +70oC)
Extended (-20oC to +80oC)
PART NUMBER
MT4LC1M16C3DJ-6
MT4LC1M16C3DJ-6 S
MT4LC1M16C3TG-6
MT4LC1M16C3TG-6 S
MT4C1M16C3DJ-6
MT4C1M16C3TG-6
None
ET 3
SUPPLY PACKAGE REFRESH
3.3V
SOJ
Standard
3.3V
SOJ
Self
3.3V
TSOP
Standard
3.3V
TSOP
Self
5V
SOJ
Standard
5V
TSOP
Standard
Part Number Example:
MT4LC1M16C3DJ-5
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
NOTE: 1. The third field distinguishes the low voltage offering:
LC designates VCC = 3.3V and C designates VCC = 5V.
2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
tRAC
tPC
tAA
tCAC
tRP
84ns
110ns
50ns
60ns
20ns
35ns
25ns
30ns
15ns
15ns
30ns
40ns
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
