PALCE16V8
Flash-Erasable Reprogrammable
CMOS PAL® Device
Features
• Up to 16 input terms and eight outputs
• 7.5 ns com’l version
5 ns tCO
5 ns tS
7.5 ns tPD
125-MHz state machine
• Active pull-up on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 90 mA max. commercial (10, 15, 25 ns)
• 10 ns military/industrial versions
7 ns tCO
10 ns tS
10 ns tPD
62-MHz state machine
— 115 mA max. commercial (7 ns)
• High reliability
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 130 mA max. military/industrial (10, 15, 25 ns)
— Proven Flash technology
• CMOS Flash technology for electrical erasability and
reprogrammability
— 100% programming and functional testing
• PCI-compliant
Functional Description
• User-programmable macrocell
The Cypress PALCE16V8 is a CMOS Flash Electrical
Erasable second-generation programmable array logic
device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
— Output polarity control
— Individually selectable for registered or combinatorial operation
Logic Block Diagram (PDIP/CDIP)
GND
I8
I7
I6
I5
I4
I3
I2
I1
CLK/I0
10
9
8
7
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
(64 x 32)
8
8
8
8
Macrocell
Macrocell
Macrocell
Macrocell
8
8
8
Macrocell
Macrocell
Macrocell
17
11
12
13
14
15
16
OE/I9
I/O0
I/O1
I/O2
I/O3
I/O4
Pin Configurations
Cypress Semiconductor Corporation
Document #: 38-03025 Rev. *A
•
20
I/O7
VCC
PLCC/LCC
Top View
I2
I1
CLK/I 0
VCC
I/O7
20
19
18
17
16
15
14
13
12
11
19
I/O6
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE/I9
3901 North First Street
I3
I4
I5
I6
I7
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10111213
I/O6
I/O5
I/O4
I/O3
I/O2
I8
GND
OE/I9
I/O0
I/O1
1
2
3
4
5
6
7
8
9
10
Macrocell
18
I/O5
DIP
Top View
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
GND
8
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
