USE GAL DEVICES FOR NEW DESIGNS
FINAL
COM’L: H-7/10/15/20
IND: H-7/10/15/20
Lattice Semiconductor
PALCE20RA10 Family
24-Pin Asynchronous EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Low power at 100 mA ICC
s TTL-level register preload for testability
s As fast as 7.5 ns maximum propagation delay
and 100 MHz fMAX (external)
s Extensive third-party software and programmer
support through FusionPLD partners
s Individually programmable asynchronous
clock, preset, reset, and enable
s 24-pin PDIP and 28-pin PLCC packages save
space
s Registered or combinatorial outputs
s 7.5 ns, 10 ns, and 15 ns versions utilize split
leadframes for improved performance
s Programmable polarity
s Programmable replacement for high-speed
CMOS or TTL logic
GENERAL DESCRIPTION
The PALCE20RA10 is an advanced PAL device built
with low-power, high-speed, electrically-erasable
CMOS technology. The PALCE20RA10 offers asynchronous clocking for each of the ten flip-flops in the device. The ten macrocells feature programmable clock,
preset, reset, and enable, and all can operate
asynchronously to other macrocells in the same device.
The PALCE20RA10 also has flip-flop bypass, allowing
any combination of registered and combinatorial
outputs.
very wide input gates available in PAL devices.
The equations are programmed into the device through
floating-gate cells in the AND logic array that can be
erased electrically.
The PALCE20RA10 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently.
Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the
Dedicated
Inputs
BLOCK DIAGRAM
Output
Enable
Preload
10
I9 – I 0
Programmable AND Array
40 x 80
4
Enable
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
4
3
Macro
Preload
I/O0
2-184
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Publication# 15434 Rev. H
Issue Date: February 1996
I/O9 15434H-1
Amendment /0
