Eclipse Family Data Sheet
• • • • • • Combining Performance, Density and Embedded RAM
1.0 Device Highlights
Flexible Programmable Logic
• .25u, 5 layer metal CMOS process
Programmable I/O
• High performance Enhanced I/O (EIO):
• 2.5 V Vcc, 2.5/3.3 V drive capable I/O
• Up to 4032 SuperCells
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• Up to 583,000 Max System Gates
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• Up to 512 I/O
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Embedded Dual Port SRAM
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Less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
8 Independent I/O Banks
3 Register Configuration: Input, Output, OE
• Up to 36-2,304 bit Dual Port High
• performance SRAM Blocks
• Up to 82,900 RAM bits
• RAM/ROM/FIFO Wizard for automatic
configuration
• Configurable and Cascadable
Advanced Clock Network
• 9 Global Clock Networks
• 1 dedicated
• 8 programmable
• 16 I/O (high drive) Networks:
Applications
2 I/O’s per bank
• 20 Quad-Net Networks: 5 per quadrant
• Signal processing operators
• Signal processing functions
• Networking / communications for VoIP
• Speech / voice processing
• Channel coding
Figure 1: Embedded Eclipse Block Diagram
EclipseTM Family Data Sheet
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