SC3048B
®
•
Quartz SAW Frequency Stability
•
Fundamental Fixed Frequency
•
Excellent Jitter and Symmetry
•
Rugged, Miniature, Surface-Mount Case
•
Low-Voltage Power Supply (3.3 VDC)
•
Directive 2002/95/EC (ROHS) Compliant by June, 2006
444.0 MHz
Differential
Sine-Wave
Clock
This digital clock is designed for use in critical timing applications. Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is made to drive 50 Ω loads.
Absolute Maximum Rating
Power Supply Voltage (VCC at Terminal 1)
Value
Units
0 to +4.0
VDC
Input Voltage (ENABLE at Terminal 8)
0 to +4.0
VDC
-40 to +85
°C
Case Temperature (Powered or Storage)
SMC-8 Case
Electrical Characteristics
Output Frequency
Characteristic
Absolute Frequency
Sym
fO
Tolerance from 444.000 MHz
Q and Q Output
1, 2
∆fO
Voltage into 50Ω (VSWR ≤ 1.2)
Notes
VO
1, 3
Operating Load VSWR
Symmetry
Minimum
443.911
Units
MHz
ppm
4.5
2:1
49
dBm
51
%
-30
dBc
-60
3, 4, 6
Nonharmonic Spurious
Maximum
444.089
±200
0.5
3, 4, 5
Harmonic Spurious
Typical
dBc
30
psP-P
Output (Disabled)
No Noise on VCC
3, 4, 6, 7
200 mVP-P from 1 MHz to ½ fO on
Q and Q Period Jitter
3, 4, 7, 8
35
psP-P
3, 9
75
mVP-P
Amplitude into 50 Ω
3
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
VIH
Input LOW Voltage
VIL
Input HIGH Current
IIH
100
VCC-0.1
KΩ
VCC
VCC
Operating Current
ICC
V
5
mA
mA
IIL
Operating Ambient Temperature
V
0.20
3
3, 9
tPD
Operating Voltage
0.0
VCC+0.1
-1
Input LOW Current
Propagation Delay
DC Power Supply
15
1
1, 3
TA
+3.13
VDC
40
mA
°C
18
1, 3
Lid Symbolization (YY = Year, WW = Week)
ms
+3.47
+70
+3.30
0
RFM SC3048B 444.00 MHz YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
2.
3.
4.
5.
Unless otherwise noted, all specifications include any combination of load
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads to
ground. (See: Typical Test Circuit.)
One or more of the following United States patents apply: 4,616,197; 4,670,681;
4,760,352.
The design, manufacturing process, and specifications of this device are subject
to change without notice.
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and
nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
6.
7.
8.
9.
Jitter and other spurious outputs induced by externally generated electrical noise
on VCC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
Applies to period jitter of Q and Q. Measurements are made with the Tektronix
CSA803 signal analyzer with at least 1000 samples.
Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half
of fO at the VCC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-9148
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: info@rfm.com
http://www.rfm.com
SC3048B-022806
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