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SY89801AMC

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仕様・特性

ClockWorks™ SY89801A FINAL HP PA-8000 CLOCK SOURCE FEATURES DESCRIPTION s s s s s 3.3V, –1.9V power suppies Differential LVPECL clock input Differential HSTL/LVPECL outputs Compatible with HP PA-8000 microprocessors Low-jitter source for all PA-8000 required timing signals s Available in 44-pin MQUAD package Micrel-Synergy's SY89801A PLL based clock generator provides, in a single chip, all the necessary clocks for HewlettPackard's PA-8000 Microprocessor. Utilizing Micrel-Synergy's advanced PLL technology, the SY89801A accepts a Positive-ECL (PECL) reference clock input at 100MHz-132MHz, and provides precisely aligned, ultra-low-jitter ratios of frequencies necessary for the operation of the processor. In addition, the SY89801A provides the "USYNC" synchronizing signals as required by the PA-8000. The frequency ratios are 1:1, 4:3, 3:2, 5:3 and 2:1. To facilitate direct interfacing to the PA-8000, the SY89801A operates across +3.3 volt and -1.9 volt supplies. The processor clock (PCLK), runway clock (RCLK) , and USYNC outputs are HSTL-compatible. Additionally, there is a PECL-compatible runway clock output (RCLKLV). The SY89801A requires only a simple external series-RC loop filter. Coupling Micrel-Synergy's advanced PLL technology with our proprietary ASSET bipolar process has produced a Timing Generator IC which meets the stringent requirements of the PA-8000 µP, while setting a new standard for performance and flexibility. 2 5 4 3 RCLKLV RCLKLV VEE REF_CLK VCC 6 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 12 13 14 35 TOP VIEW MQUAD M44-1 34 33 32 15 31 16 30 17 29 VEE PCLK1 PCLK1 PCLK2 PCLK2 VCC USYNC USYNC NC NC VCC PIN NAMES FSEL1 FSEL2 VCC NC FSEL0 RST VEE 18 19 20 21 22 23 24 25 26 27 28 VCC NC NC NC VEEA NC NC FILP FILN VCCA NC NC NC NC NC RCLK RCLK VEE NC NC REF_CLK PIN CONFIGURATION Pin Function REF_CLK, REF_CLK Differential Input Ref. Clock FILP, FILN Filter Pins (Positive & Negative) VCCA, VEEA Analog VCC, VEE RST Master Reset FSEL2-0 LVPECL Frequency Select Pins USYNC, USYNC Diff. HSTL Sync Signal for PA-8000 PCLK1-2, PCLK1-2 Diff. HSTL Processor Clock Signal RCLK, RCLK RCLKLV, RCLKLV Diff. HSTL Runway Clock Signal Diff. LVPECL Clock Signal Rev.: E 1 Amendment: /0 Issue Date: November 1998

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