June 1997
NDS8961
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance.These devices are particularly
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
3.1 A, 30 V. RDS(ON) = 0.1 Ω @ VGS = 10 V
RDS(ON) = 0.15 Ω @ VGS = 4.5 V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
____________________________________________________________________________________________
5
4
6
3
7
2
8
1
Absolute Maximum Ratings T A = 25°C unless otherwise noted
Symbol
NDS8961
Parameter
Units
VDSS
Drain-Source Voltage
30
V
VGSS
Gate-Source Voltage
±20
V
ID
Drain Current - Continuous
3.1
A
PD
Power Dissipation for Dual Operation
(Note 1a)
- Pulsed
Power Dissipation for Single Operation
10
2
(Note 1a)
1.6
(Note 1b)
1
(Note 1c)
TJ,TSTG
W
0.9
Operating and Storage Temperature Range
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
40
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS8961 Rev.D
