Very High CMR, Wide VCC Logic
Gate Optocouplers
HCPL-2201
HCPL-2211
HCPL-2231
HCPL-0201
HCNW2201
Technical Data
Features
• 10 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1000 V
(HCPL-2211/2212/0211/
2232, HCNW2211)
• Wide Operating VCC Range:
4.5 to 20 Volts
• 300 ns Propagation Delay
Guaranteed over the Full
Temperature Range
• 5 Mbd Typical Signal Rate
• Low Input Current (1.6 mA
to 1.8 mA)
• Hysteresis
• Totem Pole Output (No
Pullup Resistor Required)
• Available in 8-Pin DIP,
SOIC-8, Widebody Packages
• Guaranteed Performance
from -40°C to 85°C
• Safety Approval
UL Recognized -3750 V rms
for 1 minute (5000 V rms
for 1 minute for
HCNW22XX) per UL1577
CSA Approved
IEC/EN/DIN EN 60747-5-2
Approved with VIORM = 630
V peak (HCPL-2211/2212 Option
060 only) and VIORM = 1414
V peak (HCNW22XX only)
• MIL-PRF-38534 Hermetic
Version Available
(HCPL-52XX/62XX)
Applications
• Isolation of High Speed
Logic Systems
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
• Ground Loop Elimination
• Pulse Transformer
Replacement
• High Speed Line Receiver
• Power Control Systems
HCPL-2202
HCPL-2212
HCPL-2232
HCPL-0211
HCNW2211
Description
The HCPL-22XX, HCPL-02XX,
and HCNW22XX are opticallycoupled logic gates. The
HCPL-22XX, and HCPL-02XX
contain a GaAsP LED while the
HCNW22XX contains an AlGaAs
LED. The detectors have totem
pole output stages and optical
receiver input stages with built-in
Schmitt triggers to provide logiccompatible waveforms, eliminating the need for additional
waveshaping.
A superior internal shield on the
HCPL-2211/12, HCPL-0211,
Functional Diagram
HCPL-2201/11
HCPL-0201/11
HCNW2201/11
HCPL-2202/12
8 VCC
NC 1
8 VCC
NC 1
ANODE 2
7 VO
ANODE 2
7 NC
CATHODE 3
6 NC
CATHODE 3
6 VO
NC 4
SHIELD
5 GND
NC 4
SHIELD
5 GND
HCPL-2231/32
ANODE 1 1
8 VCC
CATHODE 1 2
7 VO1
CATHODE 2 3
6 VO2
ANODE 2 4
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
VO
HIGH
ON
LOW
OFF
5 GND
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.
