MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P−Channel and N−Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, VDD.
The input−signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS−to−TTL/DTL converter
(VDD = 5.0 V, VOL ≤ 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
•
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
Features
•
•
•
•
•
•
•
SOEIAJ−16
F SUFFIX
CASE 966
High Source and Sink Currents
High−to−Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
VIN can exceed VDD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
VDD
Parameter
16
NC
2
15
OUTF
INA
3
14
INF
OUTB
4
13
NC
INB
5
12
OUTE
OUTC
6
11
INE
INC
7
10
OUTD
VSS
8
9
IND
MARKING DIAGRAMS
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
1
OUTA
Value
Unit
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin
Input Voltage Range (DC or Transient)
−0.5 to +18.0
V
Vout
Output Voltage Range (DC or Transient)
−0.5 to VDD +
0.5
V
16
16
140xxBG
AWLYWW
MC140xxB
ALYWG
1
1
SOEIAJ−16
SOIC−16
Iin
Input Current (DC or Transient) per Pin
± 10
mA
Iout
Output Current (DC or Transient) per Pin
± 45
mA
PD
Power Dissipation, per Package (Note 1)
(Plastic)
(SOIC)
16
14
050B
ALYWG
G
mW
825
740
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high−impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9
1
1
TSSOP−16
xx
A
WL, L
YY, Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14049B/D
