TM
ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
February 2010
Data Sheet
Expanded In-System Programmability (ispXP™)
Features
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or sysCONFIG™ microprocessor interface
• Design security
Flexible Multi-Function Block (MFB)
Architecture
•
•
•
•
•
SuperWIDE™ logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
High Speed Operation
sysCLOCK™ PLL Timing Control
• 4.0ns pin-to-pin delays, 300MHz fMAX
• Deterministic timing
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
Low Power Consumption
• Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
• 1.8V core for low dynamic power
sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pulldown, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• LVTTL
Easy System Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX
Macrocells
Multi-Function Blocks
ispXPLD 5512MX
256
512
ispXPLD 5768MX ispXPLD 51024MX
768
1,024
8
16
24
32
Maximum RAM Bits
128K
256K
384K
512K
Maximum CAM Bits
48K
96K
144K
192K
2
2
2
2
sysCLOCK PLLs
tPD (Propagation Delay)
4.0ns
4.5ns
5.0ns
5.2ns
tS (Register Set-up Time)
2.2ns
2.8ns
2.8ns
3.0ns
tCO (Register Clock to Out Time)
fMAX (Maximum Operating Frequency)
2.8ns
3.0ns
3.2ns
3.7ns
300MHz
275MHz
250MHz
250MHz
Functional Gates
75K
150K
225K
300K
I/Os
141
149/193/253
193/317
317/381
256 fpBGA
208 PQFP
256 fpBGA
484 fpBGA
256 fpBGA
484 fpBGA
Packages
484 fpBGA
672 fpBGA
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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