ispGDS22/14
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
in-system programmable
Generic Digital Switch
TM
Functional Block Diagram (ispGDS22)
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
Closed only when C0=1 and C1=0
4:1 MUX
Vcc
01
10
Switch
Matrix
11
C2
Description
With a maximum tpd of 7.5ns, and a typical active Icc of only 25
mA, these devices provide maximum performance at very low
power levels. The ispGDS devices may be programmed in-system, using 5 volt only signals, through a simple 4-wire programming interface. The ispGDS devices are manufactured using
I/O Cell
I/O Cell
I/O Cell
B1
B0
I/O Cell
B3
Bank B
C0
00
The Lattice Semiconductor ispGDS™ family is an ideal solution
for reconfiguring system signal routing or replacing DIP switches
used for feature selection. With today’s demands for customer
ease of use, there is a need for hardware which is easily
reconfigured electronically without dismantling the system. The
ispGDS devices address this challenge by replacing conventional
switches with a software configurable solution. Since each I/O pin
can be set to an independent logic level, the ispGDS devices can
replace most DIP switch functions with about half the pin count,
and without the need for additional pull-up resistors. In addition
to DIP switch replacement, the ispGDS devices are useful as
signal routing cross-matrix switches. This is the only non-volatile
device on the market which can provide this flexibility.
B2
I/O Cell
B4
A10
I/O Cell
A9
B5
A8
I/O Cell
A7
B6
A6
PROGRAMMABLE
SWITCH MATRIX
I/O Cell
A5
I/O Cell
A4
B7
A3
B8
• APPLICATIONS INCLUDE:
— Software-Driven Hardware Configuration
— Multiple DIP Switch Replacement
— Software Configuration of Add-In Boards
— Configurable Addressing of I/O Boards
— Multiple Clock Source Selection
— Cross-Matrix Switch
A2
I/O Cell
• E2 CELL TECHNOLOGY
— Non-Volatile Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
I/O Cell
B10
• IN-SYSTEM PROGRAMMABLE (5-VOLT ONLY)
— Programming Time of Less Than One Second
— 4-Wire Programming Interface
— Minimum 10,000 Program/Erase Cycles
I/O Cell
A1
Bank A
• FLEXIBLE I/O MACROCELL
— Any I/O Pin Can be Input, Output, or Fixed
TTL High or Low
— Programmable Output Polarity
— Multiple Outputs Can be Driven by One Input
A0
I/O Cell
• HIGH-SPEED SWITCH MATRIX
— 7.5 ns Maximum Propagation Delay
— Typical Icc = 25 mA
— UltraMOS® Advanced CMOS Technology
B9
Features
C1
Lattice Semiconductor’s advanced non-volatile E2CMOS process
which combines CMOS with Electrically Erasable (E2) floating gate
technology. High speed erase times (<100ms) allow the devices
to be reprogrammed quickly and efficiently.
Each I/O macrocell can be configured as an input, an inverting
or non-inverting output, or a fixed TTL high or low output. Any
I/O pin can be driven by any other I/O pin in the opposite bank.
A single input can drive one or more outputs in the opposite bank,
allowing a signal (such as a clock) to be distributed to multiple destinations on the board, under software control. The I/Os accept
and drive TTL voltage levels.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor is able to deliver 100% field programmability and functionality of all Lattice Semiconductor products. In
addition, 10,000 erase/write cycles and data retention in excess
of 20 years are specified.
Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268--8037; http://www.latticesemi.com
ispgds_03
November 2003
