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ispLSI 2096/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
Output Routing Pool (ORP)
—
—
—
—
—
4000 PLD Gates
96 I/O Pins, Six Dedicated Inputs
96 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
Output Routing Pool (ORP)
C4
C3
S
B7
A1
A2
C0
GLB
Logic
Array
D Q
Global Routing Pool
(GRP)
D Q
D Q
A3
A5
A6
A7
D
B0
B1
B2
B6
B5
B4
B3
Output Routing Pool (ORP)
0919/2096
Description
EW
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
R
N
The ispLSI 2096 and 2096A are High Density Programmable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V insystem programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer nonvolatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
FO
• IN-SYSTEM PROGRAMMABLE
C1
D Q
Output Routing Pool (ORP)
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
C2
A0
A4
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—
—
—
—
—
—
—
C5
Output Routing Pool (ORP)
• HIGH DENSITY PROGRAMMABLE LOGIC
C6
ES
IG
N
Output Routing Pool (ORP)
C7
96
E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
20
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure 1). There are a total of 24 GLBs in the ispLSI 2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
U
SE
is
pL
SI
— Complete Programmable Device Can Combine
Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096_09
1
August 2006
Select devices have been discontinued.
See Ordering Information section for product status.
— ispLSI 2096A is Fully Form and Function Compatible
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
— ispLSI 2096A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
