Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
• Multiple GND pins minimize ground bounce
• Glitch–free power up/power down
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with
operation
equivalent load impedances down to 10Ω
• High drive (100mA) open collector drivers
DESCRIPTION
The 74F8962 and 74F8963 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired-OR bus. The B port
inverting drivers are low-capacitance open
collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 150mV
threshold region.
on B port
• Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE 896 futurebus
74F8962/8963
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching to 9Ω is guaranteed.
The voltage swing is much less for BTL, so is
its receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8962 and 74F8963 A ports have TTL
3-state drivers and TTL receivers with a latch
function.
standards
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
• Built–in precision band–gap reference
provides accurate receiver thresholds and
improved noise immunity
TYPE
The 74F8963 is the non-inverting version of
74F8962.
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8962
6.5ns
90mA
74F8963
5.5ns
90mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
DESCRIPTION
44–pin Quad Flat Pack1
N74F8962Y, N74F8963Y
44–pin Plastic Leaded Chip Carrier
N74F8962A, N74F8963A
Note to ordering information
1. Flatpack package is not available at this time.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
74F (U.L.)
HIGH/LOW
DESCRIPTION
LOAD VALUE
HIGH/LOW
AI0 – AI8
PNP latched inputs
1.0/0.167
20µA/100µA
B0 – B8
Data inputs with threshold circuitry
5.0/0.167
100µA/100µA
OEAB, OEBA
Output enable inputs (active low)
1.0/0.033
20µA/20µA
LEAB, LEBA
Latch enable inputs (active low)
1.0/0.033
20µA/20µA
AO0 – AO8
3–state outputs
150/40
3mA/24mA
OC/166.7
OC/100mA
B0 – B8
Open collector outputs
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
March 11, 1993
1
853–1425 09230
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
LOGIC SYMBOL FOR 74F8962
74F8962
2
3
4
5
7
8
9
10
11
13 14
15 16 17 19
20 21
22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
25
OEAB
24
LEAB
43
LEBA
44
OEBA
B0 B1 B2
42 40 38
VCC = Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
B3 B4 B5 B6 B7 B8
36
34 32
30 28 26
LOGIC SYMBOL FOR 74F8963
74F8963
2
3
4
5
7
8
9
10
11
13 14
15 16 17 19
20 21
22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
25
OEAB
24
LEAB
43
LEBA
44
OEBA
B0 B1 B2 B3 B4 B5 B6 B7 B8
VCC = Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
March 11, 1993
42 40 38
36
34 32
3
30 28 26
