32K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
IDT71V433
Features
x
x
x
x
x
x
x
32K x 32 memory configuration
Supports high performance system speed:
Commercial and Industrial:
— 11 11ns Clock-to-Data Access (50MHz)
— 12 12ns Clock-to-Data Access (50MHz)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
The IDT71V433 SRAM contains write, data-input, address and
control registers. There are no registers in the data output path (flowthrough architecture). Internal logic allows the SRAM to generate a
self-timed write based upon a decision which can be left until the
extreme end of the write cycle.
The burst mode feature offers the highest level of performance to
the system designer, as the IDT71V433 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from
the array after a clock-to-data access time delay from the rising clock
edge of the same cycle. If burst mode operation is selected (ADV=LOW),
the subsequent three cycles of output data will be available to the
user on the next three rising clock edges. The order of these three
addresses will be defined by the internal burst counter and the LBO
input pin.
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V
CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Description
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM organized as 32K x 32 with full support of various processor interfaces
including the Pentium™ and PowerPC™. The flow-through burst architecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
Pin Description
A0–A14
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chips Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1–BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock Input
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0–I/O31
Data Input/Output
I/O
Synchronous
VDD, VDDQ
Co re and I/O Power Supply (3.3V)
Power
N/A
VSS, VSSQ
Array Ground, I/O Ground
Power
N/A
3729 tbl 01
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3729/04
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
INTERNAL
ADDRESS
Burst
Sequence
CE
Burst
Logic
Q0
CLR
ADSP
Q1
2
CLK EN
ADDRESS
REGISTER
A0–A14
GW
BWE
A0, A1
32K x 32
BIT
MEMORY
ARRAY
15
A0*
A1*
A2–A14
32
15
Byte 1
Write Register
32
Byte 1
Write Driver
BW1
8
Byte 2
Write Register
Byte 2
Write Driver
BW2
8
Byte 3
Write Register
Byte 3
Write Driver
BW3
8
Byte 4
Write Register
Byte 4
Write Driver
BW4
8
CE
D
CS0
CS1
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
OE
OE
OUTPUT
BUFFER
32
I/O0–I/O31
3729 drw 01
3
6.42
.
