a
16-Bit Sigma-Delta ADC with
Programmable Post Processor
Preliminary Technical Data
The part provides an accurate on-chip 2.5V reference for
the modulator. A reference input/output function is provided to allow either the internal reference or an external
system reference to be used as the reference source for the
modulator.
The device is offered in a 44-pin PQFP package and is
designed to operate from -40oC to +85oC.
FUNCTIONAL BLOCK DIAGRAM
RY
NA L
I A
IM I C
EL H N
PR EC TA
T DA
V I N (-)
MOD
P ro g ra m m a b le
F ilte r
PRESET
FIL T E R
REF2
REF1
DV DD
DGND
FIR R O M
UN I
XTAL
CLOCK
HA LF_P W R
XTAL_OFF
X TA L
CLKIN
STBY
SYNC
SMODE1/DB15
S/P
SMODE0/DB14
SC R/DB 13
RD/W R
EN D/D B1 2
SOE/CS
CONTROL
LO G IC
CFMT/RS
DVAL/INT
C HE /D B1 1
T SI/D B 1 0
FSO/D B9
SDO/DB8
FSI/DB6
SDI/DB0
DOE/DB4
The post processor is a fully programmable core which
provides processing power of up to 130 million accumulates (MAC) per second. To program the post processor,
the user must produce a configuration file which contains
the programming data for the intended function. This file
is generated by a compiler which is available from Analog
V I N (+)
SFMT/DB5
The device contains Systolix's PulseDSP* post processor
which permits the signal conditioning characteristics to be
programmed through the parallel microprocessor interface, through a serial interface or, it may boot at poweron-reset from its internal ROM or from an external serial
EPROM.
2.5 V
REFERENCE
AGND
CHI/DB2
The AD7725 provides 16-bit performance for input
bandwidths up to 460 kHz and an output word rate of 1.2
MHz maximum. The input sample rate is set either by
the crystal oscillator or an external clock. The output is
available via a serial or parallel interface.
AD7725
CHO/DB3
The AD7725 is a complete 16-bit, sigma delta converter
with on chip user-programmable signal conditioning.
The output of the modulator is processed by three cascaded finite impulse response (FIR) filters. This is followed by a user-programmable post processor. The user
has complete control over the filter response (lowpass,
highpass, bandpass, stopband), the filter coefficients, the
decimation ratio. The post processor accepts up to 108
coefficients.
AVDD
ERR/DB1
GENERAL DESCRIPTION
Devices. The AD7725 compiler accepts filter coefficient
data as an input and automatically generate the required
device programming data.
SCO/DB7
FEATURES
Programmable Signal Conditioning
LowPass
HighPass
BandStop
BandPass
Programmable Decimation, Interpolation and Output
Word Rate
Flexible Programming Modes
Boot ROM
External EEPROM
Parallel/Serial Interface
19.2 MHz Master Clock Frequency
0 to +4V or ±2V Input Range
Power Supplies: AVDD, DVDD: +5V ± 5%
On-Chip 2.5V Voltage Reference
44-Pin PQFP
AD7725
*PulseDSP is a Trademark of Systolix
Prelim E1 2/00
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other
rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights
of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax:
617/326-8703
