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CY7C1031-8JC
CY7C1031 CY7C1032 64K x 18 Synchronous Cache RAM Features Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. • Supports 66-MHz Pentium® microprocessor cache systems with zero wait states • 64K by 18 common I/O • Fast clock-to-output times — 8.5 ns The CY7C1031 is designed for Intel® Pentium and i486 CPU-based systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1032 is architected for processors with linear burst sequences. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. • Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence (CY7C1031) • Two-bit wraparound counter supporting linear burst sequence (CY7C1032) • Separate processor and controller address strobes • Synchronous self-timed write • Direct interface with the processor and external cache controller • Asynchronous output enable • I/Os capable of 3.3V operation A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and an asynchronous output enable input provide easy control for bank selection and output three-state control. • JEDEC-standard pinout • 52-pin PLCC packaging Logic Block Diagram Pin Configuration A15 –A0 ADDR REG 64K X 9 64K X 9 RAM ARRAY RAM ARRAY WH TIMING CONTROL WL 9 9 8 9 10 11 12 13 14 15 16 17 18 19 20 OE A8 A9 A10 WH WL ADSC ADSP CS DQ8 DQ9 VCCQ VSSQ DQ10 DQ11 DQ12 DQ13 VSSQ VCCQ DQ14 DQ15 [1] DP1 16 ADV LOGIC CLK ADSP ADSC CS WH WL 9 14 2 2 ADV 9 A6 A7 DATA IN REGISTER 14 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C1031 7C1032 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 [1] DP0 DQ7 DQ6 VCCQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VCCQ DQ1 DQ0 A5 A 4 A 3 A 2 A1 A0 GND V CC A 15 A14 A13 A12 A11 16 ADV CLK PLCC Top View 18 18 DQ15 – DQ0 DP1 – DP0 OE Selection Guide 7C1031-8 7C1032-8 7C1031-10 7C1032-10 7C1031-12 8.5 10 12 ns 280 280 230 mA Maximum Access Time Maximum Operating Current Commercial Unit Note: 1. DP0 and DP1 are functionally equivalent to DQx. Cypress Semiconductor Corporation Document #: 38-05278 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 1, 2004
MOTOROLA
モトローラ（Motorola, Inc., NYSE:MOT）は、かつて存在したアメリカ合衆国の電子・通信機器メーカーである。 2011年1月4日をもって、二つの独立した公開会社であるモトローラ・モビリティ及びモトローラ・ソリューションズに分割された[1]。本社所在地はシカゴ近郊のイリノイ州シャンバーグであり、分割以降はモトローラ・ソリューションズが引き継いでいる
Motorola, Incorporated
U.S.A
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