IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
64-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
DESCRIPTION:
FEATURES:
−
−
−
−
−
−
−
−
−
−
IDT49C466
IDT49C466A
64-bit wide Flow-thruEDC™
Separate System and Memory Data Input/Output Buses
• Error Detect Time: 10ns
• Error Correct Time: 15ns
Corrects all single bit errors; Detects all double bit errors and some
multiple bit errors
Configurable 16-deep bus read/write FIFOs with flags
Simultaneous check bit generation and correction of memory data
Supports partial word writes on byte boundaries
Low noise output
Sophisticated error diagnostics and error logging
Parity generation on system data bus
208-pin Plastic Quad Flatpack
The IDT49C466/A 64-bit Flow-thruEDC is a high-speed error detection
and correction unit that ensures data integrity in memory systems. The flowthru architecture, with separate system and memory data buses, is ideally
suited for pipelined memory systems.
Implementing a modified Hamming code, the IDT49C466/A corrects all
single bit hard and soft errors, and detects all double bit errors. The read/
write FIFOs can store up to sixteen words. FIFO full and empty flags indicate
whether additional data can be written to or read from the EDC.
Check bit generation for partial word writes on byte boundaries is
supported on the IDT49C466/A.
Diagnostic features include a check bit register, syndrome registers, a
four bit error counter which logs up to fifteen errors, and an error data
register which stores the complete error data word. Parity can be generated
and checked on the system bus by the IDT49C466/A.
FUNCTIONAL BLOCK DIAGRAM
DIAGNOSTIC
& STATUS
REGISTERS
CHECK-BIT
COMPARATO R &
SYNDRO ME
GENERATOR &
ERROR
DETECTOR
ERR
ME RR
M
U
X
SD0-63
READ BUFFER
16 W ORDS BY
64
MD
LATCH
OUT
M
U
X
W RITE BACK PATH
M D0-63
W RITE
BUFFER
16 W ORDS BY
72
P0-7
CBI0-7
MD
LATCH
IN
ERROR
CORRECT
SD
LATCH
IN
PARITY
MD
CHECK-BIT
GENERATOR
MD
CHK-BIT
LATCH
M
U
X
B
Y
T
E
M
U
X
SD
LATCH
OUT
SD
CHECK-BIT
GENERATOR
SD
CHK-BIT
LATCH
CBSYN0-7
PARITY
GENERATE &
PARITY CHECK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2000
1
c
1999 Integrated Device Technology, Inc.
DSC-2617/9
