MC10111
Dual 3−Input/3−Ouput NOR
Gate
The MC10111 is designed to drive up to three transmission lines
simul− taneously. The multiple outputs of this device also allow the
wire “OR”−ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines from a single point makes
the MC10111 particularly useful in clock distribution applications
where minimum clock skew is desired. Three VCC pins are provided
and each one should be used.
• PD = 80 mW typ/gate (No Load)
• tpd = 2.4 ns typ (All Outputs Loaded)
• tr, tf = 2.2 ns typ (20%−80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP−16
L SUFFIX
CASE 620
1
16
LOGIC DIAGRAM
PDIP−16
P SUFFIX
CASE 648
2
3
4
5
6
7
MC10111L
AWLYYWW
MC10111P
AWLYYWW
1
1
12
13
14
9
10
11
PLCC−20
FN SUFFIX
CASE 775
VCC1 = PIN 1,15
VCC2 = PIN 16
VEE = PIN 8
A
WL
YY
WW
DIP
PIN ASSIGNMENT
10111
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
VCC1
1
16
VCC2
AOUT
2
15
VCC1
AOUT
3
14
BOUT
AOUT
4
13
BOUT
AIN
5
12
BOUT
AIN
6
11
BIN
AIN
7
10
BIN
VEE
8
9
BIN
Device
Package
Shipping
MC10111L
CDIP−16
25 Units / Rail
MC10111P
PDIP−16
25 Units / Rail
MC10111FN
PLCC−20
46 Units / Rail
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 8
1
Publication Order Number:
MC10111/D
