MT90826
Quad Digital Switch
Data Sheet
Features
•
January 2006
4,096 × 4,096 channel non-blocking switching at
8.192 or 16.384 Mbps
Ordering Information
MT90826AL
MT90826AG
MT90826AV
MT90826AL1
MT90826AG2
160 Pin MQFP
Trays
160 Ball PBGA
Trays
144 Ball LBGA
Trays
160 Pin MQFP*
Trays
160 Ball PBGA**
Trays
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
•
Per-channel variable or constant throughput
delay
•
Accepts 32 ST-BUS streams of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps
•
Split Rate mode provides a rate conversion option
to convert data from one rate to another rate
•
Automatic frame offset delay measurement for
ST-BUS input streams
Applications
•
Per-stream input delay programming
•
Medium switching platforms
•
Per-stream output advancement programming
•
CTI application
•
Per-channel high impedance output control
•
Voice/data multiplexer
•
Bit Error Monitoring on selected ST-BUS input
and output channels.
•
Digital cross connects
•
Per-channel message mode
•
WAN access system
•
Connection memory block programming
•
Wireless base stations
•
IEEE-1149.1 (JTAG) Test Port
•
3.3 V local I/O with 5 V tolerant inputs and TTL
compatible outputs
VDD
VSS
TMS
TDI
TDO
-40°C to +85°C
TCK
TRST
ODE
RESET
Test Port
STi0/FEi0
STi1/FEi1
•
•
•
STi31/FEi31
Parallel
Serial
to
Output
MUX
Multiple Buffer
Data Memory
Parallel
to
Serial
Converter
Converter
Connection
Memory
Internal
Registers
Timing Unit
Microprocessor Interface
PLLVDD PLLVSS CLK F0i
DS
CS
R/W
A13-A0
DTA
D15-D0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
STo0
STo1
•
•
•
STo31
