HD74HC74
Dual D-type Flip-Flops (with Preset and Clear)
ADE-205-421 (Z)
1st. Edition
Sep. 2000
Description
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level
present at thte data input is transferred to the output during the positive going transition to the clock pulse.
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.
Features
•
•
•
•
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High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Function Table
Inputs
Outputs
Preset
Clear
Clock
Data
Q
Q
L
H
X
X
H
L
H
L
X
X
L
L
L
H
H*1
X
H*
H
H
H
L
H
H
L
L
H
H
H
L
X
no change
no change
H
H
H
X
no change
no change
H
H
X
no change
no change
Note:
X
H
1
1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,
if Preset and Clear go HIGH simultaneously.
