Ne
Tolew 5V
Inp rant
u
20L ts on
V8D
GAL20LV8
Functional Block Diagram
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
— TTL-Compatible Balanced 8mA Output Drive
I/CLK
I
IMUX
I
CLK
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I
• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
I
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
PROGRAMMABLE
AND-ARRAY
(64 X 40)
• ACTIVE PULL-UPS ON ALL PINS
I
I
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
I
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
I
I
OE
I
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
IMUX
I/OE
Description
Pin Configuration
The GAL20LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL20LV8D is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
4
I
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed
in the table of the macrocell description section. GAL20LV8D
devices are capable of emulating any of these PAL architectures
with full function/fuse map compatibility.
2
28
I/O/Q
I
Vcc
NC
I/CLK
I
I
PLCC
26
25
5
I
I
I/O/Q
7
23
GAL20LV8D
NC
I
21
11
19
18
I/O/Q
I
I/OE
16
NC
14
I
I
12
I/O/Q
I/O/Q
GND
I
I/O/Q
NC
Top View
9
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I/O/Q
I/O/Q
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Low Voltage E2CMOS PLD
Generic Array Logic™
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20lv8_05
1
March 2000