RDRAM
512Mb (1024Kx16/18x32s)
Advance Information
Overview
The RDRAM device is a general purpose high-performance
memory device suitable for use in a broad range of applications
including computer memory, graphics, video, and any other
application where high bandwidth and low latency are required.
The 512/576 Mb RDRAM devices are extremely high-speed
CMOS DRAMs organized as 32M words by 16 or 18 bits. The
use of Rambus Signaling Level (RSL) technology permits
800MHz to 1600MHz transfer rates while using conventional
system and board design technologies. RDRAM devices are
capable of sustained data transfers up to 0.625ns per two bytes
(5.0 ns per sixteen bytes).
The architecture of the RDRAM devices allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and data
buses with independent row and column control yield over
95% bus efficiency. The RDRAM device’s 32 banks support
up to four simultaneous transactions.
Figure 1: 1600 MHz RDRAM CSP Package
The 512/576 Mb RDRAM devices are offered in a CSP horizontal package suitable for desktop as well as low-profile addin card and mobile applications.
Key Timing Parameters/Part Numbers
Organizationa
I/O Freq.
MHz
Timing Bin
Part
Number
1024Kx16x32s
800
45
512Ms-45-800
1024Kx16x32s
800
40
512Ms-40-800
1024Kx16x32s
1066
35
512Ms-35-1066
•
•
•Multiple low power states allows flexibility in power
consumption versus time to transition to active state
•Power-down self-refresh
Organization: 2 KB pages and 32 banks, x 16/18
•
•x18 organization allows ECC configurations or increased
storage/bandwidth
•x16 organization for low cost applications
Uses RSL for up to 1600MHz operation
DL-0205-01
1066
30
512Ms-30-1066
1024Kx16x32s
1200
32
512Ms-32-1200
1024Kx16x32s
1200
30
512Ms-30-1200
1024Kx16x32s
1333
31
512Ms-31-1333
1024Kx16x32s
1333
28
512Ms-28-1333
1024Kx16x32s
1600
31
512Ms-31-1600
1600
27
512Ms-27-1600
800
45
576Ms-45-800
800
40
576Ms-40-800
1066
35
576Ms-35-1066
1024Kx18x32s
1066
32
576Ms-32-1066
1024Kx18x32s
1066
32P
576Ms-32-1066
1024Kx18x32s
1066
30
576Ms-30-1066
1024Kx18x32s
1200
32
576Ms-32-1200
1024Kx18x32s
1200
30
576Ms-30-1200
1024Kx18x32s
1333
31
576Ms-31-1333
1024Kx18x32s
1333
28
576Ms-28-1333
1600
31
576Ms-31-1600
1024Kx18x32s
•Write buffer to reduce read latency
•3 precharge mechanisms for controller flexibility
•Interleaved transactions
Advanced power management:
1024Kx16x32s
1024Kx18x32s
•
•Up to 3.2 GB/s sustained data transfer rate
•Separate control and data buses for maximized efficiency
•Separate row and column control buses for easy scheduling and highest performance
•32 banks: four transactions can take place simultaneously
at full bandwidth data rates
Low latency features
512Ms-32P-1066
1024Kx18x32s
High sustained bandwidth per DRAM device
512Ms-32-1066
32P
1024Kx18x32s
•
32
1066
1024Kx18x32s
Features
1066
1024Kx16x32s
1024Kx16x32s
System-oriented features for mobile, graphics and large memory systems include power management, byte masking, and
x18 organization. The two data bits in the x18 organization are
general and can be used for additional storage and bandwidth
or for error correction.
1024Kx16x32s
1600
27
576Ms-27-1600
a. The bank designations are described in "Row and Column Cycle
Description" on page 17.
32s - 32 banks that use a “split” bank architecture.
Related Documentation
Datasheets for the RDRAM memory system components are
available on the Rambus website at www.rambus.com. Please
obtain the "Documentation Change History"for this datasheet.
The DCH is an integral part of the data sheet and contains the
most recent information about changes made to the published
version. Check the RDRAM website regularly for the latest
DCH and datasheet updates.
Advance Information
Rambus Confidential
Version 0.3
