MT90863
3 V Rate Conversion Digital Switch
Data Sheet
Features
September 2011
•
2,048 512 and 512 x 512 switching among
backplane and local streams
•
Rate conversion between 2.048, 4.096 and
8.192 Mb/s
•
Optional sub-rate switch configuration for
2.048 Mb/s streams
•
Per-channel variable or constant throughput
delay
•
Compatible to HMVIP and H.100 specifications
•
Automatic frame offset delay measurement
•
Per-stream frame delay offset programming
•
Per-channel message mode
•
Per-channel direction control
•
Per-channel high impedance output control
•
Non-multiplexed microprocessor interface
•
Connection memory block programming
•
3.3 V local I/O with 5 V tolerant inputs and
TTL-compatible outputs
•
IEEE-1149.1 (JTAG) Test Port
Ordering Information
MT90863AG
MT90863AL1
MT90863AG2
144 Pin PBGA
Trays
128 Pin MQFP* Tubes
144 Pin PBGA** Trays, Bake & Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40C to +85C
Applications
•
•
Voice/data multiplexer
•
Support ST-BUS, HMVIP and H.100 interfaces
VDD VSS
Backplane
Interface
CTI application
•
ODE
Medium and large switching platforms
Multiple Buffer
Data Memory
(2,048 channels)
ODE
STio0/
FEi0
STio15/
FEi15
STio16/
FEi16
STio23/
FEi23
STio24
STo0
S/P
&
P/S
Converter
Internal
Registers
P/S
Converter
Multiple Buffer
Local
Data Memory
Connection
(512 channels)
Memory High/Low
(512 locations)
STio31
C16i
F0i
C4i/C8i
Backplane
Connection
Memory
(2,048 locations)
Timing
Unit
Microprocessor Interface
F0o C4o
DS CS R/W
Local
Interface
Output
Mux
A7-A0
DTA D15-D0
STo15
STi0
Local
Interface
Multiple Buffer
Data Memory
(512 channels)
S/P
Converter
STi11
STi12
STi13
STi15
Test Port
TMS TDi TDo
STo11
STo12
STo13
TCK TRST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2011, Zarlink Semiconductor Inc. All Rights Reserved.
RESET
IC1
IC2
