MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1M Late Write HSTL
The MCM69R536 / 618 is a 1M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache, ATM switch,
Telecom, and other high speed memory applications. The MCM69R618
(organized as 64K words by 18 bits) and the MCM69R536 (organized as 32K
words by 36 bits wide) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is driven on the rising edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
Order this document
by MCM69R536/D
MCM69R536
MCM69R618
ZP PACKAGE
PBGA
CASE 999–02
•
•
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V +10%, –5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class 1 Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69R536 / 618–4.4 = 4.4 ns
MCM69R536 / 618–5 = 5 ns
MCM69R536 / 618–6 = 6 ns
MCM69R536 / 618–7 = 7 ns
• 119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
REV 2
2/24/00
© Motorola, Inc. 2000
MOTOROLA FAST SRAM
MCM69R536•MCM69R618
1
