MOTOROLA
Freescale Semiconductor, Inc.
Order this document
by MCM69L737A/D
SEMICONDUCTOR TECHNICAL DATA
MCM69L737A
MCM69L819A
Advance Information
Freescale Semiconductor, Inc...
4M Late Write LVTTL
The MCM69L737A/819A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L819A
organized as 256K words by 18 bits, and the MCM69L737A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
,
The differential CK clock inputs control the timing of read/write operations of
OR
the RAM. At the rising edge of the CK clock all addresses, write enables, and
T
synchronous selects are registered. An internal buffer and special logic enable
UC
the memory to accept write data on the rising edge of the CK clock a cycle after
D
address and control signals. Read data is available at the falling edge of the CK N
O
clock.
IC
M
The RAM uses LVTTL 3.3 V inputs and outputs.
SE
The synchronous write and byte enables allow writing to individual bytes or the
E
L
entire word.
C
IN
.
ZP PACKAGE
PBGA
CASE 999–01
A
C
Byte Write Control
ES
Single 3.3 V + 10%, – 5% Operation
E
LVTTL 3.3 V I/O (VDDQ)
FR
Register to Latch Synchronous Operation
BY
Asynchronous Output Enable
D
E
Boundary Scan (JTAG) IEEE IV
1149.1 Compatible
Differential Clock Inputs H
C
Optional x18 or x36 organization
AR = 8.5 ns
MCM69L737A/819A–8.5
MCM69L737A/819A–9 = 9 ns
MCM69L737A/819A–9.5 = 9.5 ns
• Sleep Mode Operation (ZZ Pin)
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
•
•
•
•
•
•
•
•
•
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
8/15/97
© Motorola, Inc. 1997
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69L737A•MCM69L819A
1
