April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description
Features
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V
P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. VGS(th) < 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOIC-16
SOT-223
Mark:.321
D2
S1
4
2
6
G2
3
5
D1
1
S2
SuperSOT TM -6
G1
Absolute Maximum Ratings
TA = 25oC unless other wise noted
Symbol
Parameter
N-Channel
P-Channel
Units
VDSS, VCC
Drain-Source Voltage, Power Supply Voltage
25
-25
V
VGSS, VIN
Gate-Source Voltage,
8
-8
V
ID, IO
Drain/Output Current
0.68
-0.46
A
2
-1.5
- Continuous
- Pulsed
PD
Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Tempature Ranger
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
0.9
W
0.7
-55 to 150
°C
6
kV
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
140
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
60
°C/W
© 1999 Fairchild Semiconductor Corporation
FDC6321C.RevB
Electrical Characteristics (TA = 25 OC unless otherwise noted )
SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Type
tD(on)
Turn - On Delay Time
N-Channel
N-Ch
VDD = 6 V, ID = 0.5 A,
P-Ch
VGs = 4.5 V, RGEN = 50 Ω
Gate-Drain Charge
N-Ch
8
16
9
18
P-Channel
N-Ch
17
30
P-Ch
55
110
VGen = -4.5 V, RGEN = 50 Ω
N-Ch
13
25
35
70
N-Channel
N-Ch
1.64
2.3
P-Ch
1.1
1.5
VGS = 4.5 V
N-Ch
0.38
P-Ch
0.32
VDS = -5 V,
N-Ch
0.45
ID = -0.25 A, VGS = -4.5 V
Qgd
Gate-Source Charge
nS
20
P- Channel
Qgs
Total Gate Charge
6
7
VDS= 5 V, ID = 0.5 A,
Qg
Turn - Off Fall Time
3
P-Ch
tf
Turn - Off Delay Time
Units
VDD = -6 V, ID = -0.5 A,
tD(off)
Turn - On Rise Time
Max
P-Ch
tr
Min
Typ
P-Ch
0.25
nS
nS
nS
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Drain-Source Diode Forward Voltage
N-Ch
VGS = 0 V, IS = 0.5 A
(Note)
VGS = 0 V, IS = -0.5 A
(Note)
0.3
P-Ch
VSD
Maximum Continuous Drain-Source Diode Forward Current
-0.5
N-Ch
0.83
1.2
0.69
0.85
P-Ch
-0.89
-1.2
-0.75
-0.85
TJ =125°C
TJ =125°C
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where thecase thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
FDC6321C.RevB
