Revised July 2001
FIN1031
3.3V LVDS 4-Bit High Speed Differential Driver
General Description
Features
This quad driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed transfer of clock and data.
s Greater than 400Mbs data rate
The FIN1031 can be paired with its companion receiver,
the FIN1032, or any other Fairchild LVDS receiver.
s Meets or exceeds the TIA/EIA-644 LVDS standard
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.0ns maximum propagation delay
s Low power dissipation
s Power OFF protection
s Pin compatible with equivalent RS-422 and LVPECL
devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
Package Number
FIN1031M
M16A
FIN1031MTC
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Inputs
Outputs
EN
EN
DIN
DOUT+
H
X
H
H
L
H
X
L
L
H
H
X
OPEN
L
H
X
L
H
H
L
X
L
L
L
H
X
L
OPEN
L
H
L
H
X
Z
Z
H = HIGH Logic Level
X = Don’t Care
DOUT−
L = LOW Logic Level
Z = High Impedance
Pin Descriptions
Pin Name
DIN1, DIN2, DIN3, DIN4
Description
LVTTL Data Inputs
DOUT1+, DOUT2+, DOUT3+, DOUT4+ Non-Inverting Driver Outputs
DOUT1−, DOUT2−, DOUT3−, DOUT4− Inverting Driver Outputs
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
Power Supply
GND
Ground
© 2001 Fairchild Semiconductor Corporation
DS500507
www.fairchildsemi.com
FIN1031 3.3V LVDS 4-Bit High Speed Differential Driver
July 2001
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
tPLHD
Parameter
Test Conditions
Differential Propagation Delay
Typ
Max
(Note 3)
Units
0.8
Differential Propagation Delay
HIGH-to-LOW
1.4
2.0
ns
0.8
LOW-to-HIGH
tPHLD
Min
1.4
2.0
ns
tTLHD
Differential Output Rise Time (20% to 80%)
RL = 100 Ω, CL = 10 pF,
0.6
0.85
1.2
ns
tTHLD
Differential Output Fall Time (80% to 20%)
See Figure 2 and Figure 3 (Note 7)
0.6
0.85
1.2
ns
0.4
ns
0.3
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
tSK(LH)
Channel-to-Channel Skew
tSK(HL)
(Note 4)
tSK(PP)
Part-to-Part Skew (Note 5)
fMAX
Maximum Frequency (Note 6)
tZHD
Differential Output Enable Time from Z to HIGH
2.5
5.0
ns
tZLD
Differential Output Enable Time from Z to LOW RL = 100Ω, CL = 10 pF,
2.7
5.0
ns
tHZD
Differential Output Disable Time from HIGH to Z See Figure 4 and Figure 5 (Note 7)
3.2
5.0
ns
tLZD
Differential Output Disable Time from LOW to Z
3.4
5.0
ns
1.0
200
275
ns
MHz
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, 0V to 3V, 50% Duty Cycle; Output VOD > 250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Note 7: Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
3
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FIN1031
AC Electrical Characteristics
