May 1998
FDC636P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as cellular phone and
notebook computer power management and other battery
powered circuits where high-side switching, and low in-line
power loss are needed in a very small outline surface
mount package.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
-2.8 A, -20 V. RDS(ON) = 0.130 Ω @ VGS = -4.5 V
RDS(ON) = 0.180 Ω @ VGS = -2.5 V.
SuperSOTTM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-223
SO-8
SOIC-16
S
1
D
.63
6
2
5
3
D
4
6
G
SuperSOT
TM
pin 1
-6
D
D
Absolute Maximum Ratings T A = 25°C unless otherwise noted
Symbol Parameter
FDC636P
Units
VDSS
Drain-Source Voltage
-20
V
VGSS
Gate-Source Voltage
±8
V
ID
Drain Current - Continuous
-2.8
A
PD
Maximum Power Dissipation
(Note 1a)
- Pulsed
-11
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Temperature Range
1.6
W
0.8
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
30
°C/W
© 1998 Fairchild Semiconductor Corporation
FDC636P Rev.B
Typical Electrical Characteristics
-3.5V
-3.0V
12
RDS(ON) , NORMALIZED
-I D , DRAIN-SOURCE CURRENT (A)
VGS = -4.5V
- 2.5V
9
6
- 2.0V
3
0
DRAIN-SOURCE ON-RESISTANCE
2
15
1.8
1.6
-3.0V
1.2
1
2
3
4
-3.5V
5
0
3
Figure 1. On-Region Characteristics.
6
9
12
15
0.5
I D = -1.4A
I D = - 2.8A
VGS = - 4.5V
1.4
R DS(ON)
,ON-RESISTANCE(OHM)
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-5.0V
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
125
0.4
0.3
0.2
TA = 125°C
0.1
25°C
0
150
1
2
TJ , JUNCTION TEMPERATURE (°C)
-V
GS
Figure 3. On-Resistance Variation
with Temperature.
3
4
5
,GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance Variation with
Gate-To-Source Voltage.
10
VDS = -5V
TA = -55°C
8
-I S , REVERSE DRAIN CURRENT (A)
10
-I D , DRAIN CURRENT (A)
-4.5V
-I D , DRAIN CURRENT (A)
-VDS , DRAIN-SOURCE VOLTAGE (V)
25°C
125°C
6
4
2
0
-4.0V
1
0.8
0
V GS= -2.5V
1.4
0
1
2
3
-VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
4
VGS = 0V
1
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-V SD , BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDC636P Rev.B
