November 1997
FDC6322C
Dual N & P Channel , Digital FET
General Description
Features
These dual N & P Channel logic level enhancement mode field
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage
applications as a replacement for bipolar digital transistors in
load switching applications. Since bias resistors are not
required, this dual digital FET can replace several digital
transistors with difference bias resistors.
N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V.
P-Ch 25 V, -0.46 A, RDS(ON) = 1.5 Ω @ VGS= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. VGS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOIC-16
SOT-223
Mark: .322
4
5
2
6
Absolute Maximum Ratings
3
1
TA = 25oC unless other wise noted
Symbol
Parameter
N-Channel
P-Channel
Units
VDSS, VCC
Drain-Source Voltage, Power Supply Voltage
25
-25
V
VGSS, VIN
Gate-Source Voltage,
8
-8
V
ID, IO
Drain/Output Current
- Continuous
0.22
-0.46
A
- Pulsed
0.5
-1
PD
Maximum Power Dissipation
0.9
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Tempature Ranger
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
W
0.7
-55 to 150
°C
6
kV
(Note 1a)
140
°C/W
(Note 1)
60
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
© 1997 Fairchild Semiconductor Corporation
FDC6322C.Rev B1
SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Type
tD(on)
Turn - On Delay Time
N-Channel
N-Ch
VDD = 6 V, ID = 0.5 A,
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Min
Typ
Max
Units
5
10
nS
P-Ch
7
14
VGs = 4.5 V, RGEN = 50 Ω
N-Ch
4.5
10
P-Ch
8
16
P-Channel
N-Ch
4
8
VDD = -6 V, ID = -0.5 A,
Qgd
Gate-Drain Charge
35
55
N-Channel
N-Ch
0.49
0.7
P-Ch
1
1.5
VGS = 4.5 V
N-Ch
0.22
P-Ch
0.32
VDS = -5 V, ID = -0.25 A,
N-Ch
0.07
VGS = -4.5 V
Gate-Source Charge
7
P- Channel
Qgs
VGen = -4.5 V, RGEN = 50 Ω
P-Ch
nS
90
VDS= 5 V, ID = 0.2 A,
Total Gate Charge
55
3.2
P-Ch
Qg
P-Ch
N-Ch
nS
0.25
nS
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.5 A
VGS = 0 V, IS = -0.5 A
(Note 2)
(Note 2)
0.5
P-Ch
VSD
N-Ch
-0.5
N-Ch
0.97
1.3
P-Ch
-0.88
A
V
-1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design. RθJA shown below for single device operation on FR-4 in still air.
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDC6322C.Rev B1
