November 1998
FDG6320C
Dual N & P Channel Digital FET
General Description
Features
These dual N & P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETS. Since
bias resistors are not required, this dual digital FET can
replace several different digital transistors, with different bias
resistor values.
N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 Ω @ VGS= 4.5 V,
RDS(ON) = 5.0 Ω @ VGS= 2.7 V.
P-Ch -0.14 A, -25V, RDS(ON) = 10 Ω @ VGS= -4.5V,
RDS(ON) = 13 Ω @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
SC70-6
SuperSOTTM-6
SOT-23
S2
SC70-6
Absolute Maximum Ratings
Symbol
5
3
4
D2
TA = 25oC unless other wise noted
Parameter
VDSS
S1
G1
6
2
.20
pin 1
SOIC-14
1
G2
D1
SO-8
SOT-8
N-Channel
P-Channel
Units
Drain-Source Voltage
25
-25
V
VGSS
Gate-Source Voltage
8
-8
V
ID
Drain Current
- Continuous
0.22
-0.14
A
- Pulsed
0.65
-0.4
PD
Maximum Power Dissipation
TJ,TSTG
Operating and Storage Temperature Ranger
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
(Note 1)
0.3
W
-55 to 150
°C
6
kV
415
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
© 1998 Fairchild Semiconductor Corporation
(Note 1)
FDG6320C Rev. D
Electrical Characteristics (continued)
SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Type
tD(on)
Turn - On Delay Time
N-Channel
VDD = 5 V, ID = 0.5 A ,
Min
Typ
Max
Units
N-Ch
5
12
nS
P-Ch
5
12
tr
Turn - On Rise Time
VGS = 4.5 V, RGEN = 50 Ω
N-Ch
4.5
10
P-Ch
8
16
tD(off)
Turn - Off Delay Time
P-Channel
N-Ch
4
8
VDD = -5 V, ID = -0.5 A,
P-Ch
9
18
tf
Turn - Off Fall Time
VGS = -4.5 V, RGEN = 50 Ω
N-Ch
3.2
7
P-Ch
5
12
Qg
Total Gate Charge
N-Channel
N-Ch
0.29
0.4
VDS = 5 V, ID = 0.22 A,
P-Ch
0.22
0.31
Qgs
Gate-Source Charge
VGS = 4.5 V
N-Ch
0.12
P- Channel
P-Ch
0.12
Qgd
Gate-Drain Charge
VDS = -5 V, ID = -0.14 A,
N-Ch
0.03
VGS = -4.5 V
P-Ch
0.05
nS
nS
nS
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
N-Ch
0.25
P-Ch
VGS = 0 V, IS = 0.5 A
VGS = 0 V, IS = -0.5 A
(Note 2)
(Note 2)
A
-0.25
N-Ch
0.8
1.2
P-Ch
-0.8
V
-1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum mounting pad on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6320C Rev. D
