September 2013
FDG6322C
Dual N & P Channel Digital FET
General Description
Features
These dual N & P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETs. Since
bias resistors are not required, this dual digital FET can
replace several different digital transistors, with different bias
resistor values.
N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 Ω @ VGS= 4.5 V,
RDS(ON) = 5.0 Ω @ VGS= 2.7 V.
P-Ch -0.41 A,-25V, RDS(ON) = 1.1 Ω @ VGS= -4.5V,
RDS(ON) = 1.5 Ω @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
SC70-6
SuperSOTTM-6
SOT-23
G2
SO-8
SOT-8
S2
SOIC-14
6
1
Q1
D1
5
2
pin 1
SC70-6
S1
G1
D2
Q2
3
4
Mark: .22
Absolute Maximum Ratings
Symbol
Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain Current
TA = 25oC unless other wise noted
N-Channel
P-Channel
Units
25
-25
V
8
-8
V
- Continuous
0.22
-0.41
A
- Pulsed
0.65
-1.2
PD
Maximum Power Dissipation
TJ,TSTG
Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
(Note 1)
0.3
W
-55 to 150
°C
6
kV
415
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
© 2012 Fairchild Semiconductor Corporation
(Note1)
FDG6322C Rev.F3
Electrical Characteristics (continued)
SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Type
tD(on)
Turn - On Delay Time
N-Channel
VDD = 5 V, ID = 0.5 A,
VGS = 4.5 V, RGEN = 50 Ω
tD(off)
Turn - On Rise Time
Max
Units
N-Ch
5
10
nS
P-Ch
7
15
N-Ch
4.5
10
8
16
Gate-Drain Charge
VGS = -4.5 V, RGEN = 50 Ω
N-Ch
3.2
7
35
60
N-Channel
N-Ch
0.29
0.4
P-Ch
1.1
1.5
VGS = 4.5 V
N-Ch
0.12
P-Ch
0.31
VDS = -5 V, ID = -0.41 A,
N-Ch
0.03
P-Ch
nS
80
VGS = -4.5 V
Qgd
Gate-Source Charge
8
55
P- Channel
Qgs
Total Gate Charge
4
P-Ch
VDS= 5 V, ID = 0.22 A,
Qg
N-Ch
P-Ch
Turn - Off Fall Time
P-Channel
VDD = -5 V, ID = -0.5 A,
tf
Turn - Off Delay Time
Typ
P-Ch
tr
Min
nS
0.29
nS
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.5 A
VGS = 0 V, IS = -0.5 A
N-Ch
(Note 2)
(Note 2)
0.25
P-Ch
VSD
Maximum Continuous Drain-Source Diode Forward Current
-0.25
N-Ch
0.8
1.2
P-Ch
-0.85
A
V
-1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum mounting pad on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6322C Rev.F3
