MOTOROLA
Freescale Semiconductor, Inc.
Order this document
by MCM67A618A/D
SEMICONDUCTOR TECHNICAL DATA
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Single 5 V ± 5% Power Supply
Fast Access Times: 10/12/15 ns Max
Byte Writeable via Dual Write Enables
Separate Data Input Latch for Simplified Write Cycles
Address and Chip Enable Input Latches
Common Data Inputs and Data Outputs
Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
VCC
DQ15
DQ16
DQ17
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
A6
A7
E
UW
LW
VCC
V SS
DL
AL
G
A8
A9
A10
The MCM67A618A is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18
SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability supported by multiple power pins.
Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high the device can be used as an asynchronous SRAM. When latch enables are
low the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.
Dual write enables (LW and UW) are provided to allow individually
DQ9
writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW
DQ10
controls DQ9 – DQ17 (the upper bits).
VCC
Six pair of power and ground pins have been utilized and placed on
VSS
the package for maximum performance.
DQ11
The MCM67A618A will be available in a 52–pin plastic leaded chip
DQ12
carrier (PLCC).
DQ13
This device is ideally suited for systems that require wide data bus
DQ14
widths, cache memory, and tag RAMs.
VSS
7 6 5 4 3 2 1 52 51 50 49 48
8
9
10
11
12
13
14
15
16
17
18
19
20 21 22 23 24 25 26 27 28 29 30 31 32
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
A5
A4
A3
A2
A1
A0
V SS
V CC
A15
A14
A13
A12
A11
Freescale Semiconductor, Inc...
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAM
MCM67A618A
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
AL . . . . . . . . . . . . . . . . . . . . . . Address Latch
DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Higher Byte Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be connected for proper operation of the device.
REV 1
10/9/96
© Motorola, Inc. 1996
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM67A618A
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