MOTOROLA
Freescale Semiconductor, Inc.
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by MCM67Q909/D
SEMICONDUCTOR TECHNICAL DATA
MCM67Q909
Freescale Semiconductor, Inc...
512K x 9 Bit Separate I/O
Synchronous Fast Static RAM
The MCM67Q909 is a 4M–bit static random access memory, organized as
512K words of 9 bits. It features separate TTL input and output buffers, which
drive 3.3 V output levels, and incorporates input and output registers on–board
with high speed SRAM. It also features transparent–write and data pass–through
ZP PACKAGE
capabilities.
PBGA
C.
CASE 896A–02
IN
The synchronous design allows for precise cycle control with the use of an
,
external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data
OR
output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are
T
PIN NAMES
registered on the rising edge of clock (K).
UC
D
The control pins (E, W, G) function differently in comparison to most synchronous SRAMs. This device will not deselect with E high. The RAM remains active
ON A0. –.A18. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .Address Input
Chip Enable
E . ...
C
at all times. If E is registered high, the output pins (Q0 – Q8) will be drivenIif G
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
M
is registered low. The transparent write feature allows the output data toE
track the
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
S
input data. E, G, and W must be asserted to perform a transparent write (write
D0 – D8 . . . . . . . . . . . . . . . . . . . . Data Inputs
LE next rising
and pass–through). The input data is available at the ouputs on the
Q0 – Q8 . . . . . . . . . . . . . . . . . . Data Outputs
A
edge of clock (K).
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
SC the write to the
E
The pass–through function is always enabled. E high disables
SCK . . . . . . . . . . . . . . . . . . Scan Clock Input
SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable
array while allowing a pass–through cycle to occur on the next rising edge of
RE
F
SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input
clock (K). Only a registered G high will three–state the outputs.
SDO . . . . . . . . . . . . . . . . . Scan Data Output
BY surface mount PBGA (Plastic
The MCM67Q909 is available in an 86–bump
D
VCC . . . . . . . . . . . . . . . . +5 V Power Supply
Ball Grid Array) package.
E
•
•
•
•
•
•
•
•
•
•
•
•
V
I
Single 5 V ± 5% Power Supply
CH ns Max
Fast Cycle Time: 10 nsR 12
and
A
Single Clock Operation
TTL Input and Output Levels (Outputs LVTTL Compatible)
Address, Data Input, E, W, and G Registers On–Chip
100 MHz Maximum Clock Cycle Time
Self–Timed Write
Separate Data Input and Output Pins
Transparent–Write and Pass–Through
High Output Drive Capability: 50 pF/Output at Rated Access Time
Boundary Scan Implementation
86–Bump PBGA Package for High Speed Operation
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
PIN ASSIGNMENT
A
B
2
3
4
E
1
W
VCC
G
K
A16
A14
C
D7
A15 A17
D
VSS
Q7
D5
VSS VSS
E
F
G
H
J
K
VSS
5
6
SDI SDO
VSS
A6
7
8
9
A4
A0
A2
VSS D8
VSS VSS VSS VSS
Q8
VSS
VSS VSS VSS
Q6
D6
VSS
VSS VSS VSS VSS VSS VCC
VCC
Q5
VSS VSS VSS VSS VSS
D4
Q4
D3
Q3
VSS VSS VSS VSS VSS
D2
Q2
VSS
D1
A18 VSS
D0
VSS
Q1
A12
A10 VSS
A9
A8
A5
A1
Q0
A13
A11 SCK VCC
SE
A7
A3
VSS VSS VSS
TOP VIEW
Not to Scale
REV 6
7/12/00
© Motorola, Inc. 2000
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM67Q909
1
