MOTOROLA
Freescale Semiconductor, Inc.
Order this document
by MCM67M618A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67M618A
Product Preview
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Strobes
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
TSP, TSC, and BAA Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
High Board Density 52–PLCC Package
3.3 V I/O Compatible
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
A6
A7
E
UW
LW
TSC
TSP
BAA
K
G
A8
A9
A10
The MCM67M618A is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC™ microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology. The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control signals,
except output enable (G), are clock (K) controlled through positive–edge–
triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or transfer
start cache controller (TSC) input pins. Subsequent burst addresses are generated internally by the MCM67M618A (burst sequence imitates that of the
MC68040) and controlled by the burst address advance (BAA) input pin. The
following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory.
DQ9
DQ10
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
A5
A4
A3
A2
A1
A0
VSS
VCC
A15
A14
A13
A12
A11
Freescale Semiconductor, Inc...
With Burst Counter and Self–Timed Write
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
BAA . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
TSP, TSC . . . . . . . . . . . . . . . . Transfer Start
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be
connected for proper operation of the device.
PowerPC is a trademark of IBM Corp.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/95
© Motorola, Inc. 1994
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM67M618A
1
