Freescale Semiconductor, Inc.
MOTOROLA
Order this document
by MCM67A618B/D
SEMICONDUCTOR TECHNICAL DATA
MCM67A618B
Advance Information
A6
A7
E
UW
LW
VCC
V SS
DL
AL
G
A8
A9
A10
The MCM67A618B is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18
.
SRAM core with advanced peripheral circuitry consisting of address and data
NC
input latches, active low chip enable, separate upper and lower byte write
IFN PACKAGE
strobes, and a fast output enable. This device has increased output drive capaR, PLASTIC
O CASE 778–02
bility supported by multiple power pins.
CT
Address, data in, and chip enable latches are provided. When latch enables
U
(AL for address and chip enables and DL for data in) are high, the address, data
ND
in, and chip enable latches are in the transparent state. If latch enables are tied
PIN ASSIGNMENT
O
high the device can be used as an asynchronous SRAM. When latch enables are
IC
M
low the address, data in, and chip enable latches are in the latched state. This
SEdata–in
input latch simplifies read and write cycles by guaranteeing address and
E
7 6 5 4 3 2 1 52 51 50 49 48
hold time in a simple fashion.
AL
DQ9 8
Dual write enables (LW and UW) are provided to allowC
individually
DQ10 9
bits)
writeable bytes. LW controls DQ0 – DQ8 (the lowerES while UW
VCC 10
controls DQ9 – DQ17 (the upper bits).
RE
VSS 11
Six pair of power and ground pins have beenF
DQ11 12
Y utilized and placed on
the package for maximum performance. B
DQ12 13
The MCM67A618B will be availableD a 52–pin plastic leaded chip
DQ13 14
E in
carrier (PLCC).
DQ14 15
IV
This device is ideally suited H systems that require wide data bus
VSS 16
C for
R
VCC 17
widths, cache memory, and tag RAMs.
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•
•
•
•
•
•
•
•
A
Single 5 V ±5% Power Supply
Fast Access Times: 10 ns Max
Byte Writeable via Dual Write Enables
Separate Data Input Latch for Simplified Write Cycles
Address and Chip Enable Input Latches
Common Data Inputs and Data Outputs
Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
DQ15
DQ16
DQ17
47
46
45
44
43
42
41
40
39
38
37
36
18
35
19
34
20 21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
A5
A4
A3
A2
A1
A0
V SS
V CC
A15
A14
A13
A12
A11
Freescale Semiconductor, Inc...
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAM
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
AL . . . . . . . . . . . . . . . . . . . . . . Address Latch
DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Higher Byte Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . +5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be connected for proper operation of the device.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 4
1/14/00
© Motorola, Inc. 2000
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM67A618B
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